1. Field of the Invention
The present invention relates to a processor for a computer and, more particularly, to a functional expansion of a processor having an instruction set consisting of basic instructions capable of being issued per cycle.
2. Description of the Related Art
Various microprocessors employing a RISC architecture have been commercially introduced in recent years. RISC is an acronym for Reduced Instruction Set Computer, and a RISC architecture aims to improve cost performance (cost to performance ratio) by providing an instruction set consisting only of basic and simple instructions whose frequency of use is high, and by executing an instruction sequence, optimally scheduled using compiler techniques, at high speed with simple hardware configuration.
In such a RISC architecture, the instruction length is fixed, and maximum use is made of pipeline control. Previously, only simple instruction sets were used so that all pipeline stages can be passed through in a single cycle. However, in recent RISC architectures, there is a tendency to add instructions for performing complex operations. Such instructions include, for example, those for transferring large amounts of data to enhance graphics capabilities.
When newly adding a complex instruction set to a processor designed to handle a simple instruction set, the hardware design has to be redone from scratch, which leads to the problem that the man-hours required for development increases. On the other hand, it is also practiced to handle such a complex instruction as an illegal instruction and emulate the instruction in software by causing a trap interrupt and by interpreting the instruction code by software. This, however, defeats the purpose of using a performance enhancing instruction set, since the intended increase in performance cannot be achieved because of the increased overhead due to the trap interrupt.
The present invention has been devised in view of the above problems, and an object of the invention is to provide a processor capable of supporting a complex instruction set while dramatically improving the performance compared with a method relying on software, without making major modifications to the existing hardware but by adding just a few controls and thereby emulating instructions (xcexc operation) in hardware.
To achieve the above object, according to a first aspect of the invention, there is provided a processor comprising: instruction code holding means for fetching and holding a basic instruction code capable of issuing an instruction per cycle or an expanded instruction code not capable of issuing an instruction per cycle; a first instruction decoder for issuing an instruction by decoding the basic instruction code held in the instruction code holding means; a second instruction decoder for decoding the expanded instruction code held in the instruction code holding means, and for issuing one instruction per cycle by translating the expanded instruction code into a sequence of multiple instructions; a counter for counting the number of instructions to be issued by the second instruction decoder, and for outputting a signal indicating that the expanded instruction code is being executed; instruction selecting means for selecting the instruction issued from the first instruction decoder when executing the basic instruction code and the instruction issued from the second instruction decoder when executing the expanded instruction code; execution instruction holding means for holding the instruction output from the instruction selecting means; and instruction executing means for executing the contents of the instruction held in the execution instruction holding means.
According to a second aspect of the invention, preferably the processor described in the first aspect further comprises means for inhibiting a program counter from being updated each time an instruction is issued by the second instruction decoder.
According to a third aspect of the invention, preferably the processor described in the first aspect further comprises means for detecting completion of all instructions previously issued by the first instruction decoder, and the second instruction decoder starts issuing instructions after confirming that an output of the detecting means is on.
According to a fourth aspect of the invention, preferably the processor described in the third aspect further comprises means for generating a flag that is set on when the second instruction decoder has started issuing instructions, and is set off when all the issued instructions are completed, and the first instruction decoder does not issue instructions during the on period of the flag.
According to a fifth aspect of the invention, preferably the processor described in the first aspect further comprises means for generating a signal indicating that instructions are being issued successively by the second instruction decoder, and means for generating, in accordance with the signal, a snap-shot of hardware resources each time an instruction is issued by the second instruction decoder.
According to a sixth aspect of the invention, preferably the processor described in the first aspect further comprises means for generating a flag that is set on when the first instruction is issued by the second instruction decoder, and is set off when the last of the instructions issued by the second instruction decoder is completed, and the first instruction decoder does not issue instructions during the on period of the flag.
According to a seventh aspect of the invention, preferably the processor described in the first aspect further comprises means for generating a flag that is set on when the first instruction is issued by the second instruction decoder, and is set off when the last of the instructions issued by the second instruction decoder is completed, and means for inhibiting asynchronous interrupts during the on period of the flag.
According to an eighth aspect of the invention, preferably the processor described in the first aspect further comprises means for generating a flag that is set on when the first instruction is issued by the second instruction decoder, and is set off when the last of the instructions issued by the second instruction decoder is completed, and a counter which monitors an instruction complete signal from the instruction executing means during the on period of the flag, and counts up each time the signal is set on, and when the counter has counted up to a value equal to the number of instructions to be issued by the second instruction decoder, the processor is transferred to an expanded instruction code execution complete state.
According to a ninth aspect of the invention, preferably the processor described in the first aspect further comprises means for performing control so that no interrupts occur during the issuing of instructions by the second instruction decoder, by confirming that asynchronous interrupts are not likely to occur before the instruction issued by the second instruction decoder is started.
According to a 10th aspect of the invention, preferably the processor described in the first aspect further comprises means for detecting an illegal condition of the expanded instruction code in the first instruction issue cycle of the second instruction decoder and, when an illegal condition is detected, causing an interrupt to inhibit the second instruction decoder from issuing the instruction sequence.
According to an 11th aspect of the invention, preferably the processor described in the first aspect further comprises means for detecting completion of all instructions previously issued by the first instruction decoder, and means for generating a snap-shot of hardware resources only when the second instruction decoder issues the first instruction, but not generating a snap-shot when the second instruction decoder issues the subsequent instructions.
According to a 12th aspect of the invention, preferably the processor described in the first aspect further comprises means for masking an output of an address-stopping address match detection circuit during the execution of the instructions issued by the second instruction decoder and for reporting an address match result to an interrupt control circuit when the execution of the last of the instructions issued by the second instruction decoder is completed.
According to a 13th aspect of the invention, preferably, in the processor described in any of the first to 12th aspects, the expanded instruction code to be decoded by the second instruction decoder is a block data transfer instruction code for specifying a transfer of data whose data size is an integral multiple of the data size transferrable by one basic instruction.